Dr. Steven H. Voldman is an IEEE Fellow for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.” He was the recipient of the ESD Association Outstanding Contribution Award in 2007. He received his B.S. in Eng. Science from Univ. of Buffalo (1979); a first M.S. EE (1981) from Massachusetts Institute of Technology (MIT); a second degree EE Degree (Engineer Degree) from MIT; a MS Eng. Physics (1986) and a Ph.D EE (1991) from Univ. of Vermont under IBM's Resident Study Fellow program.
Dr. Voldman was a member of the semiconductor development of IBM for 25 years. He was a member of the IBM’s Bipolar SRAM, CMOS DRAM, CMOS logic, Silicon on Insulator (SOI), BiCMOS and Silicon Germanium, RF CMOS, RF SOI, smart power technology development and image processing technology teams. In 2007, Voldman joined the Qimonda Corporation as a member of the DRAM development team, and reporting to Qimonda Europe working on 70, 58, 48 and 32 nm CMOS DRAM technology. He was responsible for ESD technology strategy, ESD and latchup design manuals, and ESD design working on ESD protection in 512 Mb, 1 Gigabit, and 2 Gigabit DRAM products. In 2008, Voldman worked as a full time ESD consultant for Taiwan Semiconductor Manufacturing Corporation (TSMC) supporting ESD and latchup development for 45 nm CMOS technology and a member of the TSMC Standard Cell Development team in Hsinchu, Taiwan. In 2009, Steve became a Senior Principal Engineer working for the Intersil Corporation working on analog, power, and RF applications in RF CMOS, RF Silicon Germanium, and SOI.
Dr. Voldman was chairman of the SEMATECH ESD Working Group, to establish a national strategy for ESD in the United States; this group initiated ESD technology benchmarking strategy, test structures and commercial test system strategy. At SEMATECH, he was responsible for establishing collaboration between the ESD Association and the JEDEC standards development, as well as launching the first TLP standard working group. He is a member of the ESD Association Board of Directors, ESDA Education Committee, as well ESD Standards Chairman for TLP and VF-TLP testing. Dr. Voldman was also the first chairman of the ESDA ESD Technology Roadmap committee and co-established the ESD Technology Roadmap in 2005. In 2005, he was the Subcommittee Chairman for both the Latchup Sub-committee for the International Reliability Physics (IRPS) and the EOS/ESD Symposium, the ESD Chairman for the International Physical and Failure Analysis (IPFA) Symposium, and presently serving on the technical program committees for the Taiwan ESD Conference (T-ESDC) 2010 in Taiwan, and ICSICT 2010 in China. Steve has provided tutorials on ESD, latchup, failure mechanisms, and RF ESD devices to the IRPS, EOS/ESD, T-ESDC, BCTM, IPFA, ASICON (China), and ICSICT (China).
Dr. Voldman is an author of the six books ESD: Physics and Devices, ESD:Circuits and Devices, ESD: Radio Frequency (RF) Technology and Circuits, Latchup, and ESD: Failure Mechanisms and Models, ESD: Design and Synthesis as well as a contributor to the book Silicon Germanium: Technology, Modeling and Design, and a chapter contributor to new text Nanoelectronics: Nanowires, Molecular Electronics, and Nano-devices.
In the ESD Association, Voldman initiated the “ESD on Campus” program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 35 universities in the United States, Singapore, Taiwan, Malaysia, Philippines, Thailand, and China. He also provides tutorials internationally on ESD protection.
Dr. Voldman has written over 150 technical papers between 1982 and 2011. He is a recipient of over 215 issued US patents. Steven Voldman provides tutorials and lectures on inventions, innovations, and patents; and has also founded a limited liability corporation (LLC) consulting business supporting ESD design, teaching, patents and patent litigation. S. Voldman served as the ESD expert witness for Acer vs Hewlett Packard.